1. Field
The present disclosure relates generally to high-speed data communications interfaces, and more particularly, to optimizing circuit designs for communications links.
2. Background
Manufacturers of mobile devices, such as cellular phones, may deploy various electronic components in one or more integrated circuit (IC) devices and/or on one or more circuit boards. The electronic components may include processing devices, storage devices, communications transceivers, display drivers, and the like. In one example, a processing device may be provided on a printed circuit board (PCB) and may communicate with one or more memory devices on the same PCB and/or on a different PCB. The processor may communicate with the memory devices using a high-speed communication link that supports unidirectional and bidirectional channels for data and control signals.
In a multi-wire interface, the maximum speed of the communication link and the ability of a receiver to reliably capture data may be limited by crosstalk from neighboring connectors. The effect of crosstalk can be diminished by increasing spacing between adjacent connectors, assignment of signals transmitted on adjacent connectors, reducing transmission clock rates and through other techniques, many of which can have negative impacts including reduced performance of the communication link, increased size of semiconductor dice, circuit boards and chip carriers. Accordingly, there is a need for tools and techniques that optimize design of communications links.